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| DATA SHEET MOS INTEGRATED CIRCUIT PD78P0308, 78P0308Y 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The PD78P0308 and 78P0308Y are members of the PD780308 and 780308Y Subseries of the 78K/0 Series, in which the on-chip mask ROM of the PD780308 and 780308Y is replaced with a one-time PROM. Because this device can be programmed by users, it is ideally suited for system evaluation, small-scale and multiple-device production, and early development and time-to-market. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD780308, 780308Y Subseries User's Manual: U11377E 78K/0 Series Instructions User's Manual: U12326E FEATURES * Pin-compatible with mask ROM version (except VPP pin) * Program memory (one-time PROM): 60 KBNote * Internal high-speed RAM: * Internal expansion RAM: * LCD display RAM: * Supply voltage: 1024 bytes 1024 bytes 40 x 4 bits VDD = 2.0 to 5.5 V Note The internal PROM capacity can be changed by setting the internal memory size switching register (IMS). Remark Refer to 1. DIFFERENCES BETWEEN PD78P0308, 78P0308Y AND MASK ROM VERSIONS for the difference between the one-time PROM and mask ROM versions. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U11776EJ2V0DS00 (2nd edition) Date Published December 2003 N CP(K) Printed in Japan The mark shows major revised points. 1996, 2003 PD78P0308, 78P0308Y ORDERING INFORMATION Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM One-time PROM One-time PROM One-time PROM One-time PROM PD78P0308GC-8EU PD78P0308YGC-8EU PD78P0308GF-3BA PD78P0308YGF-3BA 2 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 52-pin 52-pin 64-pin 64-pin 42/44-pin PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780065 PD780078 PD780034A PD780024A PD780034AS PD780024AS PD78014H EMI-noise reduced version of the PD78078 PD78078Y PD78070AY PD780018AY PD780058Y PD78058FY PD78054Y PD78054 with timer and enhanced external interface ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited functions PD78054 with enhanced serial I/O EMI-noise reduced version of the PD78054 PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A 52-pin version of the PD780024A EMI-noise reduced version of the PD78018F PD78018F PD78083 Inverter control PD78018FY Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) 64-pin PD780988 VFD drive On-chip inverter controller and UART. EMI-noise reduced. 100-pin 80-pin 80-pin 80-pin PD780208 PD780232 PD78044H PD78044F LCD drive PD78044F with enhanced I/O and VFD C/D. Display output total: 53 For panel control. On-chip VFD C/D. Display output total: 53 PD78044F with N-ch open-drain I/O. Display output total: 34 Basic subseries for driving VFD. Display output total: 34 78K/0 Series 100-pin 100-pin 120-pin 120-pin 120-pin 100-pin 100-pin 100-pin PD780354 PD780344 PD780338 PD780328 PD780318 PD780308 PD78064B PD78064 PD780354Y PD780344Y PD780344 with enhanced A/D converter PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max. PD780308Y PD78064Y PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, on-chip UART Bus interface supported 100-pin 80-pin 80-pin 80-pin 80-pin 64-pin PD780948 PD78098B PD780702Y PD780703AY PD780833Y PD780816 Meter control On-chip CAN controller PD78054 with IEBusTM controller On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function 100-pin 80-pin 80-pin PD780958 PD780852 PD780828B For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. Data Sheet U11776EJ2V0DS 3 PD78P0308, 78P0308Y The major functional differences between the subseries are shown below. * Subseries without the suffix Y Function Subseries Name Control ROM Capacity Timer 8-Bit 16-Bit Watch WDT 4 ch 1 ch 1 ch 1 ch 8-Bit 10-Bit 8-Bit A/D 8 ch A/D - D/A 2 ch 3 ch (UART: 1 ch) 88 Serial Interface I/O VDD External MIN. Expansion Value 1.8 V Yes PD78075B 32 KB to 40 KB PD78078 PD78070A 48 KB to 60 KB - 61 2 ch 3 ch (time-division UART: 1 ch) 3 ch (UART: 1 ch) 68 69 2.7 V 1.8 V 2.7 V 2.0 V PD780058 24 KB to 60 KB PD78058F 48 KB to 60 KB PD78054 16 KB to 60 KB PD780065 40 KB to 48 KB PD780078 48 KB to 60 KB PD780034A 8 KB to 32 KB PD780024A PD780034AS PD780024AS 2 ch 1 ch 8 ch - 4 ch 8 ch - 4 ch - - 8 ch - 4 ch (UART: 1 ch) 3 ch (UART: 2 ch) 3 ch (UART: 1 ch) 60 52 51 2.7 V 1.8 V 39 - PD78014H PD78018F 8 KB to 60 KB PD78083 Inverter control VFD drive 8 KB to 16 KB - 3 ch Note - - 1 ch 2 ch 53 Yes 1 ch (UART: 1 ch) - 8 ch - 3 ch (UART: 2 ch) 33 47 4.0 V - Yes PD780988 16 KB to 60 KB PD780208 32 KB to 60 KB PD780232 16 KB to 24 KB PD78044H 32 KB to 48 KB PD78044F 16 KB to 40 KB 2 ch 3 ch 2 ch 1 ch - 1 ch 1 ch - 1 ch 1 ch 8 ch 4 ch 8 ch - - 2 ch 74 40 2.7 V 4.5 V 2.7 V - 1 ch 2 ch 68 LCD drive PD780354 24 KB to 32 KB PD780344 PD780338 48 KB to 60 KB PD780328 PD780318 PD780308 48 KB to 60 KB PD78064B 32 KB PD78064 16 KB to 32 KB 4 ch 1 ch 1 ch 1 ch - 8 ch 8 ch - - 3 ch (UART: 1 ch) 66 1.8 V - 3 ch 2 ch - 10 ch 1 ch 2 ch (UART: 1 ch) 54 62 70 2 ch 1 ch 8 ch - - 3 ch (time-division UART: 1 ch) 2 ch (UART: 1 ch) 57 2.0 V Bus PD780948 60 KB 2 ch 2 ch 1 ch 2 ch 1 ch 1 ch 8 ch - - 2 ch 3 ch (UART: 1 ch) 79 69 4.0 V 2.7 V 4.0 V 2.2 V 4.0 V Yes - interface PD78098B 40 KB to 60 KB supported PD780816 32 KB to 60 KB Meter control PD780958 48 KB to 60 KB Dashboard PD780852 32 KB to 40 KB control 4 ch 3 ch 12 ch - 1 ch 1 ch 1 ch - 5 ch - - - - - 2 ch (UART: 1 ch) 2 ch (UART: 1 ch) 3 ch (UART: 1 ch) 46 69 56 59 2 ch 1 ch - - PD780828B 32 KB to 60 KB Note 16-bit timer: 2 channels 10-bit timer: 1 channel 4 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y * Subseries with the suffix Y Function Subseries Name Control ROM Capacity 48 KB to 60 KB - - 2 ch Timer 8-Bit 10-Bit 8-Bit A/D - D/A 2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 3 ch (I2C: 1 ch) 88 61 88 1.8 V Serial Interface I/O VDD External 8-Bit 16-Bit Watch WDT A/D 4 ch 1 ch 1 ch 1 ch 8 ch MIN. Value Expansion 1.8 V 2.7 V Yes PD78078Y PD78070AY PD780018AY 48 KB to 60 KB PD780058Y PD78058FY PD78054Y PD780078Y 24 KB to 60 KB 2 ch 3 ch (time-division 68 UART: 1 ch, I2C: 1 ch) 3 ch (UART: 1 ch, I2C: 1 ch) 2 ch - 8 ch - 4 ch (UART: 2 ch, I2C: 1 ch) 3 ch (UART: 1 ch, 8 ch - I2C: 1 ch) 2 ch (I2C: 1 ch) 53 66 52 69 48 KB to 60 KB 16 KB to 60 KB 48 KB to 60 KB 2.7 V 2.0 V 1.8 V PD780034AY 8 KB to 32 KB PD780024AY PD78018FY LCD drive 8 KB to 60 KB 24 KB to 32 KB 4 ch 1 ch 51 PD780354Y PD780344Y PD780308Y PD78064Y 1 ch 1 ch 1 ch - 8 ch 8 ch - - 4 ch (UART: 1 ch, I2C: 1 ch) 1.8 V - 48 KB to 60 KB 2 ch 3 ch (time-division 57 UART: 1 ch, I2C: 1 ch) 2 ch (UART: 1 ch, I2C: 1 ch) 2.0 V 16 KB to 32 KB - - Bus PD780702Y 60 KB 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (UART: 1 ch, I2C: 1 ch) 67 3.5 V - interface PD780703AY 59.5 KB supported PD780833Y 60 KB 65 4.5 V Remark The functions of the subseries without the suffix Y and the subseries with the suffix Y are the same, except for the serial interface (if a subseries without the suffix Y is available). Data Sheet U11776EJ2V0DS 5 PD78P0308, 78P0308Y OVERVIEW OF FUNCTIONS Item Internal memory One-time PROM High-speed RAM Expansion RAM LCD display RAM General-purpose registers Minimum instruction execution time When main system clock is selected When subsystem clock is selected Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, Boolean operation) * BCD adjustment, etc. I/O ports (Segment signal output pins included) A/D converter LCD controller/driver Total: * CMOS input: * CMOS I/O: 57 2 55 122 s (@ 32.768 kHz operation) 60 KBNote 1024 bytes 1024 bytes 40 x 4 bits 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time variable function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 MHz operation) PD78P0308 PD78P0308Y 8-bit resolution x 8 channels * Segment signal output: 40 pins maximum * Common signal output: 4 pins maximum * Bias: 1/2,1/3 bias convertible * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable: 1 channel 1 channel 2 channels 1 channel 1 channel Serial interface * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable: 1 channel * 3-wire serial I/O mode: * 3-wire serial I/O/UART mode selectable: 1 channel Timer * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: * Watch timer: * Watchdog timer: Timer output Clock output 3 pins (14-bit PWM output enable: 1 pin) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0 MHz operation with main system clock) 32.768 kHz (@ 32.768 kHz operation with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz (@ 5.0 MHz operation with main system clock) Note The internal PROM capacity can be changed by setting the internal memory size switching register (IMS). 6 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Item Vectored interrupt sources Test input Supply voltage Package Maskable Non-maskable Software Internal: 1 1 Internal: 1, External: 1 VDD = 2.0 to 5.5 V * 100-pin plastic LQFP (fine pitch) (14 x 14) * 100-pin plastic QFP (14 x 20) PD78P0308 Internal: 13, External: 6 PD78P0308Y Data Sheet U11776EJ2V0DS 7 PD78P0308, 78P0308Y PIN CONFIGURATIONS (TOP VIEW) (1) Normal operating mode * 100-pin plastic LQFP (fine pitch) (14 x 14) PD78P0308GC-8EU, 78P0308YGC-8EU P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 VDD0 AVREF P100 P101 VSS1 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P110/S13 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT2 XT1/P07 VDD1 X1 X2 VPP P72/SCK2/ASCK P71/SO2/TXD P10/ANI0 AVSS P117 P116 P115 P114/RXD P113/TXD P112/SCK3 P111/SO3 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P70/SI2/RxD P27/SCK0[/SCL] P26/SO0/SB1[/SDA1] P25/SI0/SB0[/SDA0] P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 COM3 BIAS VLC0 VLC1 S11 S12 S13 S14 S15 S16 S17 S9 S10 Cautions 1. 2. Connect the VPP pin directly to VSS0 or VSS1. Connect the AVSS pin to VSS0. Remarks 1. [ ]: PD78P0308Y only 2. When the device is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 8 VLC2 VSS0 S0 S1 S2 S3 S4 S5 S6 S7 S8 Data Sheet U11776EJ2V0DS S18 PD78P0308, 78P0308Y * 100-pin plastic QFP (14 x 20) PD78P0308GF-3BA, 78P0308YGF-3BA P25/SI0/SB0[/SDA0] P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 P26/SO0/SB1[/SDA1] P27/SCK0[/SCL] P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK VPP X2 X1 VDD1 XT1/P07 XT2 RESET P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 VSS0 VLC2 VLC1 VLC0 BIAS COM3 COM2 COM1 COM0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P05/INTP5 P110/SI3 P111/SO3 P112/SCK3 P113/TXD P114/RXD P115 P116 P117 AVSS P10/ANI0 P11/ANI1 P12/ANI2 P15/ANI5 AVREF P30/TO0 P31/TO1 P32/TO2 P33/TI1 P13/ANI3 P14/ANI4 P16/ANI6 P17/ANI7 P34/TI2 P36/BUZ P35/PCL P101 P102 P103 P100 VDD0 Cautions 1. 2. Connect the VPP pin directly to VSS0 or VSS1. Connect the AVSS pin to VSS0. Remarks 1. [ ]: PD78P0308Y only 2. When the device is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. VSS1 P37 Data Sheet U11776EJ2V0DS 9 PD78P0308, 78P0308Y ANI0 to ANI7: ASCK: AVREF: AVSS: BIAS: BUZ: Analog input Asynchronous serial clock Analog reference voltage Analog ground LCD power supply bias control Buzzer clock RxD: S0 to S39: SB0, SB1: SCK0, SCK2, SCK3: SCL: SDA0, SDA1: SI0, SI2, SI3: SO0, SO2, SO3: TI00, TI01: TI1, TI2: TO0 to TO2: TxD: VDD0, VDD1: VLC0 to VLC2: VPP: VSS0, VSS1: X1, X2: XT1, XT2: Receive data Segment output Serial bus Serial clock Serial clock Serial data Serial input Serial output Timer input Timer input Timer output Transmit data Power supply LCD power supply Programming power supply Ground Crystal (main system clock) Crystal (subsystem clock) COM0 to COM3: Common output INTP0 to INTP5: External interrupt input P00 to P05, P07: Port 0 P10 to P17: P25 to P27: P30 to P37: P70 to P72: P80 to P87: P90 to P97: P100 to P103: P110 to P117: PCL: RESET: Port 1 Port 2 Port 3 Port 7 Port 8 Port 9 Port 10 Port 11 Programmable clock Reset 10 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (2) PROM programming mode * 100-pin plastic LQFP (fine pitch) (14 x 14) PD78P0308GC-8EU, 78P0308YGC-8EU RESET Open (L) VDD (L) Open VPP PGM (L) A9 (L) 1 2 3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CE OE (L) (L) (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) 4 5 6 7 VDD VDD (L) VSS (L) D0 D1 D2 D3 D4 D5 D6 D7 (L) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (L) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Cautions 1. 2. 3. 4. (L): VSS: Open: Independently connect to VSS via a pull-down resistor. Connect to GND. Leave open. RESET: Set to low level. (L) Data Sheet U11776EJ2V0DS 11 PD78P0308, 78P0308Y * 100-pin plastic QFP (14 x 20) PD78P0308GF-3BA, 78P0308YGF-3BA 1 2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 (L) 3 4 5 (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 VPP Open (L) VDD (L) Open 6 7 8 9 10 11 12 13 14 15 16 RESET A9 (L) PGM (L) OE CE (L) 17 18 19 20 21 22 23 24 25 (L) 26 27 28 29 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD VDD (L) (L) VSS Cautions 1. 2. 3. 4. A0 to A16: CE: D0 to D7: OE: PGM: (L): VSS: Open: Independently connect to VSS via a pull-down resistor. Connect to GND. Leave open. RESET: VDD: VPP: VSS: Reset Power supply Programming power supply Ground RESET: Set to low level. Address bus Chip enable Data bus Output enable Program 12 Data Sheet U11776EJ2V0DS (L) D0 D1 D2 D3 D4 D5 D6 D7 PD78P0308, 78P0308Y BLOCK DIAGRAM TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 P00 Port 0 P01 to P05 P07 TO1/P31 TI1/P33 TO2/P32 TI2/P34 8-bit timer/event counter 1 Port 1 8-bit timer/event counter 2 Port 2 Watchdog timer Port 3 Watch timer Port 7 SI0/SB0[/SDA0]/P25 SO0/SB1[/SDA1]/P26 SCK0[/SCL]/P27 P70 to P72 P30 to P37 P25 to P27 P10 to P17 16-bit timer/ event counter Serial interface 0 Port 8 P80 to P87 SI2/RxD/P70 SO2/TxD/P71 RxD/P114 TxD/P113 SCK2/ASCK/P72 Serial interface 2 78K/0 CPU core PROM (60 KB) Port 9 P90 to P97 Port 10 P100 to P103 SI3/P110 SO3/P111 SCK3/P112 Port 11 Serial interface 3 P110 to P117 S0 to S23 ANI0/P10 to ANI7/P17 AVSS AVREF A/D converter RAM (2048 bytes) S24/P97 to S31/P90 S32/P87 to S39/P80 LCD controller/driver COM0 to COM3 VLC0 to VLC2 INTP0/P00 to INTP5/P05 Interrupt control BIAS fLCD RESET X1 X2 XT1/P07 XT2 BUZ/P36 Buzzer output System control PCL/P35 Clock output control VDD0, VDD1 VSS0, VSS1 VPP Remark [ ]: PD78P0308Y only Data Sheet U11776EJ2V0DS 13 PD78P0308, 78P0308Y CONTENTS 1. DIFFERENCES BETWEEN PD78P0308, 78P0308Y AND MASK ROM VERSIONS ................. 2. PIN FUNCTIONS ............................................................................................................................ 2.1 Pins in Normal Operating Mode ......................................................................................... 2.2 Pins in PROM Programming Mode ..................................................................................... 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................... 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ......................................................... 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ........................................... 5. PROM PROGRAMMING ................................................................................................................ 5.1 Operating Modes .................................................................................................................. 5.2 PROM Write Procedure ........................................................................................................ 5.3 PROM Read Procedure ........................................................................................................ 6. ONE-TIME PROM VERSION SCREENING ................................................................................... 7. ELECTRICAL SPECIFICATIONS .................................................................................................. 8. PACKAGE DRAWINGS .................................................................................................................. 9. RECOMMENDED SOLDERING CONDITIONS ............................................................................. APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. APPENDIX B. RELATED DOCUMENTS ............................................................................................ 15 16 16 19 20 24 25 26 26 28 32 32 33 61 63 64 70 14 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 1. DIFFERENCES BETWEEN PD78P0308, 78P0308Y AND MASK ROM VERSIONS The PD78P0308 and 78P0308Y are single-chip microcontrollers with an on-chip one-time PROM to which a program can be written only once. It is possible to make all the functions except for the PROM specifications and the mask option of LCD drive power supply dividing resistor the same as those of mask ROM versions by setting the internal memory size switching register (IMS). Differences between the one-time PROM versions (PD78P0308, 78P0308Y) and mask ROM versions (PD780306, 780308, 780306Y, 780308Y) are shown in Table 1-1. Table 1-1. Differences Between PD78P0308, 78P0308Y and Mask ROM Versions Item Internal ROM configuration Internal ROM capacity Internal ROM capacity change by the internal memory size switching register (IMS) IC pin VPP pin Mask options of LCD drive power supply dividing resistor Serial interface (SBI) Serial interface (I2C) Electrical specifications, recommended soldering conditions Provided Not provided Not provided Provided Provided Not provided Not provided Provided No Yes None Yes No Available PD78P0308 One-time PROM 60 KB PossibleNote PD78P0308Y Mask ROM Versions PD780308 Subseries PD780308Y Subseries Mask ROM PD780306, 780306Y: 48 KB PD780308, 780308Y: 60 KB Impossible Refer to the data sheet of the individual product. Note The internal PROM capacity is set to 60 KB by RESET input. Caution There are differences in noise immunity and noise radiation between the one-time PROM and mask ROM versions. When pre-producing an application set with a one-time PROM version and then mass-producing it with a mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM version. Data Sheet U11776EJ2V0DS 15 PD78P0308, 78P0308Y 2. PIN FUNCTIONS 2.1 Pins in Normal Operating Mode (1) Port pins (1/2) Pin Name P00 P01 P02 P03 P04 P05 P07Note 1 P10 to P17 Input I/O Port 1 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings.Note 2 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 I/O I/O Port 2 3-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. Port 3 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. Input SO0/SB1[/SDA1] SCK0[/SCL] TO0 TO1 TO2 TI1 TI2 PCL BUZ -- Input SI0/SB0[/SDA0] I/O Input I/O Port 0 7-bit I/O port Function Input only Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. Input only Input Input After Reset Input Input Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0 to ANI7 Notes 1. 2. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1, and be sure not to use the feedback resistor of the subsystem clock oscillator. When the P10/ANI0 to P17/ANI7 pins are used as the analog inputs for the A/D converter, shift port 1 to input mode. The on-chip pull-up resistors are automatically disabled. Remark [ ]: PD78P0308Y only 16 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (1) Port pins (2/2) Pin Name P70 P71 P72 P80 to P87 I/O I/O I/O Port 7 3-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. Port 8 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. The I/O port/segment signal output function is specifiable in 2-bit units by the LCD display control register (LCDC). P90 to P97 I/O Port 9 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. The I/O port/segment signal output function is specifiable in 2-bit units by the LCD display control register (LCDC). P100 to P103 I/O Port 10 4-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. It is possible to directly drive LEDs. P110 P111 P112 P113 P114 P115 to P117 I/O Port 11 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. Falling edge detection is possible. Input SI3 SO3 SCK3 TXD RXD -- Input -- Input S31 to S24 Input S39 to S32 SO2/TXD SCK2/ASCK Function After Reset Input Alternate Function SI2/RXD Data Sheet U11776EJ2V0DS 17 PD78P0308, 78P0308Y (2) Non-port pins (1/2) Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI2 SI3 SO0 SO2 SO3 SB0 SB1 SDA0 SDA1 SCK0 SCK2 SCK3 SCL RxD TxD ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ S0 to S23 S24 to S31 S32 to S39 COM0 to COM3 VLC0 to VLC2 BIAS Output -- -- LCD controller/driver common signal output. LCD drive voltage. LCD drive power supply. Output -- -- Output Output Output Output Input Output Input Input I/O Serial interface serial clock input/output. Input I/O Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Serial interface serial data input. Input I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. After Reset Input Alternate Function P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0[/SDA0] P70/RxD P110 P26/SB1[/SDA1] P71/TxD P111 P25/SI0[/SDA0] P26/SO0[/SDA1] P25/SI0/SB0 P26/SO0/SB1 P27[/SCL] P72/ASCK P112 PD78P0308Y only PD78P0308Y only Asynchronous serial interface serial data input. Asynchronous serial interface serial data output. Asynchronous serial interface serial clock input. External count clock input to 16-bit timer (TM0). Capture trigger signal input to capture register (CR00). External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2). 16-bit timer (TM0) output (also used for 14-bit PWM output). 8-bit timer (TM1) output. 8-bit timer (TM2) output. Clock output (for main system clock, subsystem clock trimming). Buzzer output. LCD controller/driver segment signal output. Input Output Input Input Input Input Input Input Input P27/SCK0 P70/SI2, P114 P71/SO2, P113 P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 -- P97 to P90 P87 to P80 -- -- -- Remark [ ]: PD78P0308Y only 18 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (2) Non-port pins (2/2) Pin Name ANI0 to ANI7 AVREF AVSS RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 VPP I/O Input Input -- Input Input -- Input -- -- -- -- -- -- Function A/D converter analog input. A/D converter reference voltage input (also used for analog power supply). A/D converter ground potential. Set to the same potential as VSS0. System reset input. Crystal resonator connection for main system clock oscillation. Crystal resonator connection for subsystem clock oscillation. Positive power supply for ports. Ground potential for ports. Positive power supply (except for ports and analog). Ground potential (except for ports and analog). High voltage application in program write/verify mode. Connect directly to VSS0 or VSS1 in normal operating mode. Input -- -- -- -- -- -- -- -- -- -- P07 -- -- -- -- -- -- -- -- -- -- After Reset Input -- Alternate Function P10 to P17 -- 2.2 Pins in PROM Programming Mode Pin Name I/O Input PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. Function RESET VPP A0 to A16 D0 to D7 CE OE PGM VDD VSS Input Input I/O Input Input Input -- -- PROM programming mode setting and high voltage application during program write/verification. Address bus. Data bus. PROM enable input/program pulse input. Read strobe input to PROM. Program/program inhibit input in PROM programming mode. Positive power supply. Ground potential. Data Sheet U11776EJ2V0DS 19 PD78P0308, 78P0308Y 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The types of pin I/O circuits and the recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of I/O circuit, see Figure 2-1. Table 2-1. Type of I/O Circuit of Each Pin (1/2) Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0 to P17/ANI7 P25/SI0/SB0[/SDA0] P26/SO0/SB1[/SDA1] P27/SCK0[/SCL] P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P80/S39 to P87/S32 P90/S31 to P97/S24 P100 to P103 P110/SI3 P111/SO3 P112/SCK3 P113/TXD P114/RXD P115 to P117 S0 to S23 COM0 to COM3 17-B 18-A Output Leave open. 5-H 8-C Input: Independently connect to VDD0 via a resistor. Output: Leave open. 8-C 5-H 8-C 17-C 5-H 8-C 5-H 16 11-B 10-B Input I/O Connect to VDD0. Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. I/O Circuit Type 2 8-C I/O I/O Input Input: Recommended Connection of Unused Pins Connect to VSS0. Independently connect to VSS0 via a resistor. Output: Leave open. Remark [ ]: PD78P0308Y only 20 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Table 2-1. Type of I/O Circuit of Each Pin (2/2) Pin Name VLC0 to VLC2 BIAS RESET XT2 AVREF AVSS VPP Connect directly to VSS0 or VSS1. 2 16 -- Input -- -- Leave open. Connect to VSS0. -- I/O Circuit Type -- I/O -- Recommended Connection of Unused Pins Leave open. Data Sheet U11776EJ2V0DS 21 PD78P0308, 78P0308Y Figure 2-1. List of Pin I/O Circuits (1/2) Type 2 Type 10-B VDD0 Pull-up enable IN Data VDD0 P-ch P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Open drain Output disable N-ch VSS0 Type 5-H Pull-up enable VDD0 Data VDD0 Type 11-B Pull-up enable Data VDD0 P-ch P-ch VDD0 P-ch IN/OUT P-ch IN/OUT Output disable P-ch N-ch VSS0 Comparator + - VSS0 N-ch Output disable Input enable AVSS N-ch VREF (threshold voltage) Input enable VDD0 Type 16 Feedback cut-off P-ch Type 8-C Pull-up enable VDD0 Data P-ch P-ch IN/OUT Output disable N-ch VSS0 XT1 XT2 22 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Figure 2-1. List of Pin I/O Circuits (2/2) Type 17-B VLC0 VLC1 N-ch P-ch SEG data P-ch VLC2 N-ch VSS1 N-ch OUT Type 17-C VDD0 P-ch Pull-up enable VDD0 Data P-ch IN/OUT Output disable VSS0 Input enable N-ch P-ch Type 18-A VLC0 VLC0 VLC1 P-ch N-ch P-ch N-ch SEG data OUT VLC2 P-ch VLC2 N-ch VSS1 VSS1 N-ch P-ch N-ch P-ch VLC1 N-ch P-ch COM data N-ch P-ch Data Sheet U11776EJ2V0DS 23 PD78P0308, 78P0308Y 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) This is a register used to disable use of part of the internal memory by software. By setting the internal memory size switching register (IMS), it is possible to get the same memory map as that of the mask ROM versions with a different internal memory (ROM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 3-1. Format of Internal Memory Size Switching Register Symbol IMS 7 RAM2 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0H After reset CFH R/W R/W ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection 1 1 1 1 0 1 0 1 48 KB 60 KB Setting prohibited Other than above RAM2 RAM1 RAM0 Internal high-speed RAM capacity selection 1024 bytes Setting prohibited 1 1 0 Other than above Table 3-1 shows the setting values of IMS that make the memory mapping the same as that of the mask ROM versions. Table 3-1. Internal Memory Size Switching Register Setting Values Target Mask ROM Versions IMS Setting Value CCH CFH PD780306, 780306Y PD780308, 780308Y 24 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) This register is used to set the internal expansion RAM capacity by software. By setting the internal expansion RAM size switching register (IXS), it is possible to get the same memory map as that of the mask ROM versions with a different internal expansion RAM capacity. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Figure 4-1. Format of Internal Expansion RAM Size Switching Register Symbol IXS 7 0 6 0 5 0 4 0 3 IXRAM3 2 IXRAM2 1 IXRAM1 0 IXRAM0 Address FFF4H After reset 0AH R/W W IXRAM3 1 IXRAM2 0 IXRAM1 1 IXRAM0 0 Internal expansion RAM capacity selection 1024 bytes Setting prohibited Other than above Table 4-1 shows the setting values of IXS that make the memory mapping the same as that of the mask ROM versions. Table 4-1. Internal Expansion RAM Size Switching Register Setting Values Target Mask ROM Versions IXS Setting Value 0AH PD780306, 780306Y PD780308, 780308Y Data Sheet U11776EJ2V0DS 25 PD78P0308, 78P0308Y 5. PROM PROGRAMMING The PD78P0308 and 78P0308Y have an on-chip 60 KB PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to PIN CONFIGURATIONS (2) PROM programming mode. Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be specified). They cannot be written by a PROM programmer that cannot specify the write address. 5.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE, and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 5-1. Operating Modes of PROM Programming Pin Operating Mode Page data latch Page write Byte write Program verify Program inhibit L +12.5 V +6.5 V H H L L x x Read Output disable Standby +5 V +5 V L L H L H H L H L L H x H L L H H L H x x Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance RESET VPP VDD CE OE PGM D0 to D7 x: L or H 26 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, data can be read from any device by controlling the OE pin, if multiple PD78P0308 and 78P0308Ys are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1-page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, write and verification operations should be executed X times (X 10) repeatedly. (6) Byte write mode Byte write is executed when a 0.1 ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, write and verification operations should be executed X times (X 10) repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if the write operation was performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple PD78P0308 and 78P0308Ys are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device whose PGM pin is driven high. Data Sheet U11776EJ2V0DS 27 PD78P0308, 78P0308Y 5.2 PROM Write Procedure Figure 5-1. Page Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X = 10 ? Yes X=X+1 0.1 ms program pulse Verify 4 bytes Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Fail Pass Verify all bytes All pass Write end Fail Defective product G = Start address N = Program last address 28 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Figure 5-2. Page Program Mode Timing Page data latch Page program Program verify A2 to A16 A0, A1 Hi-Z D0 to D7 Data input VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Data output Data Sheet U11776EJ2V0DS 29 PD78P0308, 78P0308Y Figure 5-3. Byte Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 0.1 ms program pulse Address = Address + 1 Fail Verify Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD No X = 10 ? Yes Pass Verify all bytes All pass Write end Fail Defective product G = Start address N = Program last address 30 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Figure 5-4. Byte Program Mode Timing Program Program verify A0 to A16 D0 to D7 Hi-Z Data input Data output VPP VPP VDD VDD VDD + 1.5 VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. 2. 3. VDD should be applied before VPP, and cut after VPP. VPP should not exceed +13.5 V, including overshoot. Disconnection during application of +12.5 V to VPP may have an adverse effect on reliability. Data Sheet U11776EJ2V0DS 31 PD78P0308, 78P0308Y 5.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown below. (1) Fix the RESET pin to low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in PIN CONFIGURATIONS (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to the A0 to A16 pins. (4) Read mode (5) Output data to the D0 to D7 pins. The timing of steps (2) to (5) above is shown in Figure 5-5. Figure 5-5. PROM Read Timing A0 to A16 Address input CE (input) OE (input) D0 to D7 Hi-Z Data output Hi-Z 6. ONE-TIME PROM VERSION SCREENING The one-time PROM versions (PD78P0308GC-8EU, 78P0308GF-3BA, 78P0308YGC-8EU, and 78P0308YGF3BA) cannot be tested completely by NEC Electronics before they are shipped, because of their structure. It is recommended to perform screening to verify PROM after writing the necessary data and performing high-temperature storage under the conditions below. Storage Temperature 125C Storage Time 24 hours 32 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD VPP AVREF AVSS Input voltage VI1 P00 to P05, P07, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117, X1, X2, XT2, RESET VI2 Output voltage Analog input voltage Output current, high VO VAN IOH P10 to P17 Per pin Total for P01 to P05, P10 to P17, P25 to P27, P70 to P72, P110 to P117 Total for P30 to P37, P80 to P87, P90 to P97, P100 to P103 Output current, low IOL Per pin Peak value r.m.s. value Total for P01 to P05, P10 to P17, P110 to P117 Total for P30 to P37, P100 to P103 Total for P25 to P27, P70 to P72, P80 to P87, P90 to P97 Operating ambient temperature Storage temperature TA Tstg Peak value r.m.s. value Peak value r.m.s. value Peak value r.m.s. value 30 15Note 60 40 Note Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 Unit V V V V V A9 PROM programming mode -0.3 to +13.5 -0.3 to VDD + 0.3 V V V mA mA Analog input pin AVSS - 0.3 to AVREF + 0.3 -10 -15 -15 mA mA mA mA mA mA mA mA mA C C 140 100Note 50 20 Note -40 to +85 -65 to +150 Note The root mean square (r.m.s.) value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Capacitance (TA = 25C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. MIN. TYP. MAX. 15 15 15 Unit pF pF pF Data Sheet U11776EJ2V0DS 33 PD78P0308, 78P0308Y Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0Note 4 to 5.5 V) Resonator Recommended Circuit Ceramic resonator VPP X2 R1 C2 C1 X1 Oscillation frequency Oscillation stabilization timeNote 2 Crystal resonator VPP X2 R1 C2 C1 X1 Oscillation frequency (fX)Note 1 (fX)Note 1 VDD = Oscillation voltage range After VDD reaches oscillation voltage range MIN. VDD = Oscillation voltage range 4.5 V VDD 5.5 V Note 3 timeNote 2 2.0 V VDD < 4.5 V Note 3 Parameter Conditions MIN. TYP. MAX. Unit 1.0 5.0 MHz 4 ms 1 5 MHz Oscillation stabilization 10 30 1.0 5.0 ms External clock X2 X1 X1 input frequency (fX)Note 1 MHz X1 input high-/lowlevel width (tXH, tXL) 85 500 ns Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. 3. After VDD reaches oscillation voltage range MIN. 4. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or higher). Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 34 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0Note 4 to 5.5 V) Resonator Recommended Circuit Crystal resonator VPP XT1 XT2 R2 C3 C4 Oscillation frequency (fXT)Note 1 Oscillation stabilization XT1 input XT1 XT2 frequency (fXT)Note 1 XT1 input high-/lowlevel width (tXTH, tXTL) 5 15 timeNote 2 VDD = Oscillation voltage range 4.5 V VDD 5.5 VNote 3 2.0 V VDD < 4.5 VNote 3 32 1.2 2 10 100 kHz s 32 32.768 35 kHz Parameter Conditions MIN. TYP. MAX. Unit External clock s Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. 3. After VDD reaches oscillation voltage range MIN. 4. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or higher). Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U11776EJ2V0DS 35 PD78P0308, 78P0308Y DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Input voltage, high Symbol VIH1 Conditions P10 to P17, P30 to P32, P35 to P37, P80 to P87, P90 to P97, P100 to P103 VIH2 P00 to P05, P25 to P27, P33, P34, P70 to P72, P110 to P117, RESET VIH3 X1, X2 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V VIH4 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 VNote Input voltage, low VIL1 P10 to P17, P30 to P32, P35 to P37, P80 to P87, P90 to P97, P100 to P103 VIL2 P00 to P05, P25 to P27, P33, P34, P70 to P72, P110 to P117, RESET VIL3 X1, X2 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V VIL4 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V Output voltage, high Output voltage, low P01 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P110 to P117 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, open-drain, pulled up (R = 1 k) VOL3 IOL = 400 A 0.5 V 0.2VDD V VOL1 VOH VDD = 4.5 to 5.5 V, IOH = -1 mA IOH = -100 A P100 to P103 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA 0.4 V Note MIN. 0.7VDD 0.8VDD 0.8VDD 0.85VDD VDD - 0.5 VDD - 0.2 0.8VDD 0.9VDD 0.9VDD 0 0 0 0 0 0 0 0 0 VDD - 1.0 VDD - 0.5 TYP. MAX. VDD VDD VDD VDD VDD VDD VDD VDD VDD 0.3VDD 0.2VDD 0.2VDD 0.15VDD 0.4 0.2 0.2VDD 0.1VDD 0.1VDD VDD VDD Unit V V V V V V V V V V V V V V V V V V V V V 0.6 2.0 Note Remark When the XT1/P07 pin is used as P07, input the inverse phase of P07 to the XT2 pin. Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 36 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117, RESET ILIH2 Input leakage current, low ILIL1 VIN = 0 V X1, X2, XT1/P07, XT2 P00 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117, RESET ILIL2 Output leakage current, high Output leakage current, low Software pull-up resistor R VIN = 0 V P01 to P05, P10 to P17, P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 Supply currentNote 1 IDD1 5.00 MHz crystal oscillation (fXX = 2.5 MHz)Note 2 operating mode 5.00 MHz crystal oscillation (fXX = 5.0 IDD2 MHz)Note 3 operating mode 5.00 MHz crystal oscillation (fXX = 2.5 MHz)Note 2 HALT mode 5.00 MHz crystal oscillation (fXX = 5.0 MHz)Note 3 HALT mode IDD3 32.768 kHz crystal oscillation operating modeNote 4 IDD4 32.768 kHz crystal oscillation HALT modeNote 4 IDD5 XT1 = VDD STOP mode When feedback resistor is connected IDD6 XT1 = VDD STOP mode When feedback resistor is disconnected VDD = 5.0 V 10%Note 5 VDD = 3.0 V 10%Note 6 VDD = 2.2 V 10%Note 6 VDD = 5.0 V 10%Note 5 VDD = 3.0 V 10%Note 6 VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.2 V 10% 5 0.7 0.4 9 1 1.4 500 280 1.6 650 135 95 70 25 5 2.5 1 0.5 0.3 0.1 0.05 0.05 15 2.1 1.2 27 3 4.2 1500 840 4.8 1950 270 190 140 55 15 12.5 30 10 10 30 10 10 mA mA mA mA mA mA 15 45 90 k ILOL VOUT = 0 V -3 ILOH VOUT = VDD X1, X2, XT1/P07, XT2 -20 3 20 -3 MIN. TYP. MAX. 3 Unit A A A A A A A A mA A A A A A A A A A A A A A Notes 1. Current flowing to the VDD pin. Not including the current flowing to the A/D converter, on-chip pull-up resistors, or LCD dividing resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. When the main system clock is stopped. 5. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 04H) Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U11776EJ2V0DS 37 PD78P0308, 78P0308Y LCD Controller/Driver Characteristics (at Normal Operation) (1) Static display mode (TA = -10 to +85C, VDD = 2.0 to 5.5 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote deviationNote (common) VODS IO = 1 A Symbol VLCD RLCD VODC IO = 5 A VLCD0 = VLCD 2.0 V VLCD VDD 0 0.2 V Conditions MIN. 2.0 60 0 100 TYP. MAX. VDD 150 0.2 Unit V k V LCD output voltage (segment) Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (2) 1/3 bias method (TA = -10 to +85C, VDD = 2.5 to 5.5 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote deviationNote (common) VODS IO = 1 A Symbol VLCD RLCD VODC IO = 5 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.5 V VLCD VDD 0 0.2 V Conditions MIN. 2.5 60 0 100 TYP. MAX. VDD 150 0.2 Unit V k V LCD output voltage (segment) Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (3) 1/2 bias method (TA = -10 to +85C, VDD = 2.7 to 5.5 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote deviationNote (common) VODS IO = 1 A Symbol VLCD RLCD VODC IO = 5 A VLCD0 = VLCD VLCD1 = VLCD x 1/2 VLCD2 = VLCD1 2.7 V VLCD VDD 0 0.2 V Conditions MIN. 2.7 60 0 100 TYP. MAX. VDD 150 0.2 Unit V k V LCD output voltage (segment) Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). 38 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y LCD Controller/Driver Characteristics (at Low-Voltage Operation) (1) Static display mode (TA = -10 to +85C, 2.0 V VDD < 3.4 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote (common) LCD output voltage deviationNote (segment) VODS IO = 1 A Symbol VLCD RLCD VODC IO = 5 A VLCD0 = VLCD 2.0 V VLCD VDD 0 0.2 V Conditions MIN. 2.0 60 0 100 TYP. MAX. VDD 150 0.2 Unit V k V Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (2) 1/3 bias method (TA = -10 to +85C, 2.0 V VDD < 3.4 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviationNote deviationNote (common) VODS IO = 1 A Symbol VLCD RLCD VODC IO = 5 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.0 V VLCD VDD 0 0.2 V Conditions MIN. 2.0 60 0 100 TYP. MAX. VDD 150 0.2 Unit V k V LCD output voltage (segment) Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (3) 1/2 bias method (TA = -10 to +85C, 2.0 V VDD < 3.4 V) Parameter LCD drive voltage LCD dividing resistor LCD output voltage deviation Note Symbol VLCD RLCD VODC IO = 5 A IO = 1 A Conditions MIN. 2.0 60 TYP. MAX. VDD Unit V k V 100 150 0.2 0.2 VLCD0 = VLCD VLCD1 = VLCD x 1/2 0 (common) VODS LCD output voltage deviationNote (segment) VLCD2 = VLCD1 2.0 V VLCD VDD 0 V Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). Data Sheet U11776EJ2V0DS 39 PD78P0308, 78P0308Y AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Cycle time (Min. instruction execution time) Symbol TCY Conditions Operating on main system clock (fXX = 2.5 MHz)Note 1 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V MIN. 0.8 2.0 0.4 0.8 40Note 3 0 122 TYP. MAX. 64 64 32 32 125 1/tTI00 Unit s s s s s MHz Operating on main system clock (fXX = 5.0 MHz)Note 2 Operating on subsystem clock TI00 input frequency TI00 input high-/ low-level width fTI00 tTI00 = tTIH00 + tTIL00 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V INTP0 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V 2.0 V VDD < 2.7 V INTP1 to INTP5, P110 to P117 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V tTIH00, tTIL00 2/fsam + 0.1Note 4 2/fsam + 0.2Note 4 2/fsam + 0.5Note 4 0 0 10 20 0 0 100 1.8 2/fsam + 0.1Note 4 2/fsam + 0.2Note 4 2/fsam + 0.5Note 4 10 20 10 20 4 275 100 50 s s s kHz kHz TI01 input frequency TI01 input high-/ low-level width TI1, TI2 input frequency TI1, TI2 input high-/ low-level width Interrupt request input high-/lowlevel width fTI01 tTIH01, tTIL01 fTI1 s s MHz kHz ns tTIH1, tTIL1 tINTH, tINTL s s s s s s s s RESET low-level width tRSL Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 2. Main system clock fXX = fX operation (when OSMS is set to 01H) 3. This is the value when the external clock is used. The value is 114 s (min.) when the crystal resonator is used. 4. In combination with bits 0 (SCS0) and 1 (SCS1) of the sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4). 40 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y TCY vs. VDD (at main system clock fXX = fX/2 operation) TCY vs. VDD (at main system clock fXX = fX operation) 60 60 32 Cycle time TCY [s] Guaranteed operation range Cycle time TCY [s] 10 10 Guaranteed operation range 2.0 2.0 1.0 0.8 0.4 1.0 0.8 0.4 0 1 2 2.7 3 4 5 6 0 1 2 3 3.5 4 5 6 Supply voltage VDD [V] Supply voltage VDD [V] Data Sheet U11776EJ2V0DS 41 PD78P0308, 78P0308Y (2) Serial interface (TA = -40 to +85C, VDD = 2.0 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0...internal clock output) Parameter SCK0 cycle time Symbol tKCY1 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK0 high-/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKSI1 tKSO1 C = 100 pFNote MIN. 800 1600 3200 tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns Note C is the load capacitance of SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0...external clock input) Parameter SCK0 cycle time Symbol tKCY2 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK0 high-/low-level width tKH2, tKL2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise, fall time tR2, tF2 1000 ns tSIK2 tKSI2 tKSO2 C = 100 pFNote MIN. 800 1600 3200 400 800 1600 100 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns Note C is the load capacitance of SO0 output line. 42 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (iii) SBI mode (SCK0...internal clock output): PD78P0308 only Parameter SCK0 cycle time Symbol tKCY3 Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tSBL tKCY3 ns tKSB tSBK tSBH tKSO3 R = 1 k, C = 100 pFNote 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 0 0 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns tKSI3 tKH3, tKL3 tSIK3 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V MIN. 800 3200 tKCY3/2 - 50 tKCY3/2 - 150 100 300 tKCY3/2 TYP. MAX. Unit ns ns ns ns ns ns ns Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (iv) SBI mode (SCK0...external clock input): PD78P0308 only Parameter SCK0 cycle time Symbol tKCY4 Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V SCK0 high-/low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK0 rise, fall time tR4, tF4 1000 ns tSBL tKCY4 ns tKSB tSBK tSBH tKSO4 R = 1 k, C = 100 pFNote 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 0 0 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns tKSI4 tKH4, tKL4 tSIK4 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V MIN. 800 3200 400 1600 100 300 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns ns ns Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. Data Sheet U11776EJ2V0DS 43 PD78P0308, 78P0308Y (v) 2-wire serial I/O mode (SCK0...internal clock output) Parameter SCK0 cycle time Symbol tKCY5 R = 1 k, C = 100 pFNote SCK0 high-level width tKH5 Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V MIN. 1600 3200 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns 2.7 V VDD 5.5 V tKCY5/2 - 160 2.0 V VDD < 2.7 V tKCY5/2 - 190 4.5 V VDD 5.5 V tKCY5/2 - 50 2.0 V VDD < 4.5 V tKCY5/2 - 100 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 300 350 400 600 SCK0 low-level width tKL5 SB0, SB1 setup time (to SCK0) tSIK5 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSI5 tKSO5 300 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) 2-wire serial I/O mode (SCK0...external clock input) Parameter SCK0 cycle time Symbol tKCY6 Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V SCK0 high-level width tKH6 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V SCK0 low-level width tKL6 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SCK0 rise, fall time tR6, tF6 tKSO6 R = 1 k, C = 100 pFNote 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 0 0 300 500 1000 ns ns ns tKSI6 tKCY6/2 ns tSIK6 MIN. 1600 3200 650 1300 800 1600 100 TYP. MAX. Unit ns ns ns ns ns ns ns Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. 44 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (vii) I2C bus mode (SCL...internal clock output): PD78P0308Y only Parameter SCL cycle time Symbol tKCY7 R = 1 k, C = 100 SCL high-level width tKH7 pFNote Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V SCL low-level width tKL7 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width tSBK tSBH 400 500 ns ns tKSB tKSO7 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 0 0 200 300 500 ns ns ns tKSI7 tSIK7 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V MIN. 10 20 tKCY7 - 160 tKCY7 - 190 tKCY7 - 50 tKCY7 - 100 200 300 0 TYP. MAX. Unit s s ns ns ns ns ns ns ns Note R and C are the load resistance and load capacitance of SCL, SDA0, and SDA1 output lines. (viii) I2C bus mode (SCL...external clock input): PD78P0308Y only Parameter SCL cycle time SCL high-/low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width SCL rise, fall time tR8, tF8 1000 ns tSBK tSBH 400 500 ns ns tKSB tKSO8 R = 1 k, C = 100 pFNote 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 0 0 200 300 500 ns ns ns tKSI8 0 ns Symbol tKCY8 tKH8, tKL8 tSIK8 Conditions MIN. 1000 400 200 TYP. MAX. Unit ns ns ns Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output lines. Data Sheet U11776EJ2V0DS 45 PD78P0308, 78P0308Y (b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2...internal clock output) Symbol tKCY9 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK2 high-/low-level width tKH9, tKL9 SI2 setup time (to SCK2) tSIK9 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI2 hold time (from SCK2) SO2 output delay time from SCK2 tKSI9 tKSO9 C = 100 pFNote MIN. 800 1600 3200 tKCY9/2 - 50 tKCY9/2 - 100 100 150 300 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns Parameter SCK2 cycle time Note C is the load capacitance of SCK2 and SO2 output lines. (ii) 3-wire serial I/O mode (SCK2...external clock input) Parameter SCK2 cycle time Symbol tKCY10 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK2 high-/low-level width tKH10, tKL10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 SCK2 rise, fall time tR10, tF10 1000 ns tSIK10 tKSI10 tKSO10 C = 100 pF Note MIN. 800 1600 3200 400 800 1600 100 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns 300 ns Note C is the load capacitance of SO2 output line. 46 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (iii) UART mode (dedicated baud rate generator output) Parameter Transfer rate Symbol Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. TYP. MAX. 78125 39063 19531 Unit bps bps bps (iv) UART mode (external clock input) Parameter ASCK cycle time Symbol tKCY11 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V ASCK high-/low-level width tKH11, tKL11 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V Transfer rate 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V ASCK rise, fall time tR11, tF11 MIN. 800 1600 3200 400 800 1600 39063 19531 9766 1000 TYP. MAX. Unit ns ns ns ns ns ns bps bps bps ns Data Sheet U11776EJ2V0DS 47 PD78P0308, 78P0308Y (c) Serial interface channel 3 (i) 3-wire serial I/O mode (SCK3...internal clock output) Symbol tKCY12 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SCK3 high-/low-level width tKH12, tKL12 SI3 setup time (to SCK3) tSIK12 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI3 hold time (from SCK3) SO3 output delay time from SCK3 tKSI12 tKSO12 C = 100 pFNote MIN. 800 1600 3200 tKCY12/2 - 50 tKCY12/2 - 100 100 150 300 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns Parameter SCK3 cycle time Note C is the load capacitance of SCK3 and SO3 output lines. (ii) 3-wire serial I/O mode (SCK3...external clock input) Parameter Symbol tKCY13 Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 400 800 1600 100 400 C = 100 pFNote 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns SCK3 cycle time SCK3 high-/low-level width tKH13, tKL13 SI3 setup time (to SCK3) SI3 hold time (from SCK3) SO3 output delay time from SCK3 SCK3 rise, fall time tSIK13 tKSI13 tKSO13 tR13, tF13 1000 ns Note C is the load capacitance of SO3 output line. 48 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y AC Timing Test Points (Excluding X1, XT1 Inputs) 0.8VDD 0.2VDD Test points 0.8VDD 0.2VDD Clock Timing 1/fX tXL tXH VDD - 0.5 V 0.4 V X1 input 1/fXT tXTL XT1 input tXTH VIH4 (MIN.) VIL4 (MAX.) TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI1 tTIL1 tTIH1 TI1, TI2 Data Sheet U11776EJ2V0DS 49 PD78P0308, 78P0308Y Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tRn SCK0, SCK2, SCK3 tSIKm tKSIm tKHm tFn SI0, SI2, SI3 tKSOm Input data SO0, SO2, SO3 Output data m = 1, 2, 9, 10, 12, 13 n = 2, 10, 13 SBI mode (bus release signal transfer, PD78P0308 only): tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer, PD78P0308 only): tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4 SB0, SB1 tKSO3, 4 50 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 2-wire serial I/O mode: tKCY5, 6 tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 tKSI5, 6 tKH5, 6 tF6 SB0, SB1 I2C bus mode (PD78P0308Y only): tF8 SCL tR8 tKCY7, 8 tKSB tSIK7, 8 tKSO7, 8 tSBK tKSB tKL7, 8 SDA0, SDA1 tSBH tSBK tKH7, 8 tKSI7, 8 UART mode: tKCY11 tKL11 tR11 ASCK tKH11 tF11 Data Sheet U11776EJ2V0DS 51 PD78P0308, 78P0308Y A/D Converter Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V) Parameter Resolution Overall errorNote 1 2.7 V AVREF 5.5 V 2.2 V AVREF < 2.7 V Conversion time tCONV 2.7 V AVREF 5.5 V 2.2 V AVREF < 2.7 V Sampling time Analog input voltage Reference voltage AVREF-AVSS resistance AVREF current tSAMP VIAN AVREF RAIREF AIREF When A/D conversion not operating When A/D conversion operatingNote 2 When A/D conversion not operatingNote 3 19.1 38.2 24/fXX AVSS 2.2 4 14 2.5 0.5 5.0 1.5 AVREF VDD Symbol Conditions MIN. 8 TYP. 8 MAX. 8 0.6 1.4 200 200 Unit bit %FSR %FSR s s s V V k mA mA Notes 1. Quantization error (1/2 LSB) is not included. This is expressed as a percentage (%FSR) to the full-scale value. 2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1. 3. Indicates current flowing to AVREF pin when the CS bit of ADM is 0. 52 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Data retention supply current IDDDR VDDDR = 1.6 V Subsystem clock stop and feedback resistor disconnected. Release signal set time Oscillation stabilization wait time tSREL tWAIT Release by RESET Release by interrupt request 0 2 /fx Note 17 Symbol VDDDR Conditions MIN. 1.6 TYP. MAX. 5.5 Unit V 0.1 10 A s s s Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD STOP instruction execution RESET VDDDR tSREL tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode STOP mode Operating mode Data retention mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR tSREL tWAIT Data Sheet U11776EJ2V0DS 53 PD78P0308, 78P0308Y Interrupt Request Input Timing tINTL tINTH INTP0 to INTP5 RESET Input Timing tRSL RESET 54 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y PROM Programming Characteristics DC Characteristics (1) PROM write mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current Symbol VIH VIL VOH VOL ILI VPP VDD IPP IDD PGM = VIL IOH = -1 mA IOL = 1.6 mA 0 VIN VDD -10 12.2 6.25 12.5 6.5 Conditions MIN. 0.7VDD 0 VDD - 1.0 0.4 +10 12.8 6.75 50 50 TYP. MAX. VDD 0.3VDD Unit V V V V A V V mA mA (2) PROM read mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V) Parameter Input voltage, high Input voltage, low Output voltage, high Symbol VIH VIL VOH1 VOH2 Output voltage, low Input leakage current Output leakage current VPP supply voltage VDD supply voltage VPP supply current VDD supply current VOL ILI ILO VPP VDD IPP IDD VPP = VDD CE = VIL, VIN = VIH IOH = -1 mA IOH = -100 A IOL = 1.6 mA 0 VIN VDD 0 VOUT VDD, OE = VIH -10 -10 VDD - 0.6 4.5 VDD 5.0 Conditions MIN. 0.7VDD 0 VDD - 1.0 VDD - 0.5 0.4 +10 +10 VDD + 0.6 5.5 100 50 TYP. MAX. VDD 0.3VDD Unit V V V V V A A V V A mA Data Sheet U11776EJ2V0DS 55 PD78P0308, 78P0308Y AC Characteristics (1) PROM write mode (a) Page program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Address setup time (to OE) OE setup time CE setup time (to OE) Input data setup time (to OE) Address hold time (from OE) Symbol tAS tOES tCES tDS tAH tAHL tAHV Input data hold time (from OE) Data output float delay time from OE VPP setup time (to OE) VDD setup time (to OE) Program pulse width Valid data delay time from OE OE pulse width during data latching PGM setup time CE hold time OE hold time tDH tDF tVPS tVDS tPW tOE tLW tPGMS tCEH tOEH 1 2 2 2 Conditions MIN. 2 2 2 2 2 2 0 2 0 1.0 1.0 0.095 250 0.105 1 250 TYP. MAX. Unit s s s s s s s s ns ms ms ms s s s s s (b) Byte program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Address setup time (to PGM) OE setup time CE setup time (to PGM) Input data setup time (to PGM) Address hold time (from OE) Input data hold time (from PGM) Data output float delay time from OE VPP setup time (to PGM) VDD setup time (to PGM) Program pulse width Valid data delay time from OE OE hold time Symbol tAS tOES tCES tDS tAH tDH tDF tVPS tVDS tPW tOE tOEH 2 Conditions MIN. 2 2 2 2 2 2 0 1.0 1.0 0.095 0.105 1 250 TYP. MAX. Unit s s s s s s ns ms ms ms s s 56 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y (2) PROM read mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V) Parameter Data output delay time from address Data output delay time from CE Data output delay time from OE Data output float delay time from OE Data hold time from address Symbol tACC tCE tOE tDF tOH Conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = OE = VIL 0 0 MIN. TYP. MAX. 800 800 200 60 Unit ns ns ns ns ns (3) PROM programming mode setting (TA = 25C, VSS = 0 V) Parameter PROM programming mode setup time Symbol tSMA Conditions MIN. 10 TYP. MAX. Unit s Data Sheet U11776EJ2V0DS 57 PD78P0308, 78P0308Y PROM Write Mode Timing (Page Program Mode) Page data latch Page program Program verify A2 to A16 tAS A0, A1 tDS D0 to D7 Hi-Z tDH Hi-Z tPGMS Data output tDF Hi-Z tAHL tAHV tVPS VPP VPP VDD tVDS VDD + 1.5 VDD VDD Data input tOE tAH tCES VIH CE VIL VIH PGM VIL tLW VIH OE VIL tOES tPW tCEH tOEH 58 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y PROM Write Mode Timing (Byte Program Mode) Program Program verify A0 to A16 tAS Hi-Z tDS VPP VPP VDD tVPS VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL tOES tOE tCES tPW tVDS tOEH Hi-Z tDH tDF Hi-Z tAH D0 to D7 Data input Data output Cautions 1. VDD should be applied before VPP, and cut after VPP. 2. VPP should not exceed +13.5 V, including overshoot. 3. Disconnection during application of 12.5 V to VPP may have an adverse effect on reliability. PROM Read Mode Timing A0 to A16 Valid address VIH CE VIL tCE VIH OE VIL tACCNote 1 D0 to D7 Hi-Z tOENote 1 tOH Data output Hi-Z tDFNote 2 Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE the maximum of tACC - tOE. 2. tDF is the time from when either OE or CE first reaches VIH. Data Sheet U11776EJ2V0DS 59 PD78P0308, 78P0308Y PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0 to A16 Valid address 60 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 8. PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S CD Q R 100 1 26 25 F G P H I M J K S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 +7 3 -3 1.60 MAX. S100GC-50-8EU, 8EA-2 Data Sheet U11776EJ2V0DS 61 PD78P0308, 78P0308Y 100-PIN PLASTIC QFP (14x20) A B 80 81 51 50 detail of lead end S CD Q R 100 1 31 30 F G H I M J P K S N S L M NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. P100GF-65-3BA1-4 62 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y 9. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 9-1. Surface Mounting Type Soldering Conditions (1) 100-pin plastic QFP (14 x 20) PD78P0308GF-3BA, 78P0308YGF-3BA Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 Caution Do not use different soldering methods together (except for partial heating). (2) 100-pin plastic LQFP (fine pitch) (14 x 14) PD78P0308GC-8EU, 78P0308YGC-8EU Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Recommended Condition Symbol IR35-107-2 VPS VP15-107-2 Partial heating - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Do not use different soldering methods together (except for partial heating). Caution Data Sheet U11776EJ2V0DS 63 PD78P0308, 78P0308Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are provided for system development using the PD78P0308 and 78P0308Y. Also refer to (6) Precautions When Using Development Tools. (1) Software Package SP78K0 CD-ROM in which development tools (software) common to 78K/0 Series products are integrated in one package (2) Language Processing Software RA78K0 CC78K0 DF780308 CC78K0-L Assembler package common to 78K/0 Series products C compiler package common to 78K/0 Series products Device file for PD780308 and 780308Y Subseries products (part number: SxxxxDF78064) C compiler library source file common to 78K/0 Series products (3) PROM Write Tools PG-1500 PA-78P0308GC PA-78P0308GF PG-1500 controller Control program for the PG-1500 PROM programmer Programmer adapter connected to the PG-1500 (4) Debugging Tools * When using IE-78K0-NS or IE-78K0-NS-A as in-circuit emulator IE-78K0-NS IE-78K0-NS-PA IE-78K0-NS-A IE-70000-MC-PS-B IE-70000-98-IF-C In-circuit emulator common to 78K/0 Series products Performance board to enhance/expand functions of IE-78K0-NS Combination of IE-78K0-NS and IE-78K0-NS-PA Power supply unit for IE-78K0-NS Adapter required when using a PC-9800 series (excluding notebook-type PCs) as the host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable required when using a notebook type PC as the host machine (PCMCIA socket supported) IE-70000-PC-IF-C Adapter required when using an IBM PC/ATTM compatible as the host machine (ISA bus supported) IE-70000-PCI-IF-A IE-780308-NS-EM1 NP-100GC NP-H100GC-TQ NP-100GF NP-100GF-TQ NP-H100GF-TQ TGC-100SDW Conversion adapter to connect the NP-100GC or NP-H100GC-TQ and a target system board made to be mounted on a 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Conversion socket to connect the NP-100GF and a target system board made to be mounted on a 100-pin plastic QFP (GF-3BA type) TGF-100RBP Conversion socket to connect the NP-100GF-TQ or NP-H100GF-TQ and a target system board made to be mounted on a 100-pin plastic QFP (GF-3BA type) ID78K0-NS SM78K0 DF780308 Integrated debugger for the IE-78K0-NS and IE-78K0-NS-A System simulator common to 78K/0 Series products Device file for PD780308 and 780308Y Subseries products (part number: SxxxxDF78064) Data Sheet U11776EJ2V0DS Adapter required when using a PC with an on-chip PCI bus as the host machine Emulation board to emulate PD780308 and 780308Y Subseries products Emulation probe for a 100-pin plastic LQFP (GC-8EU type) Emulation probe for a 100-pin plastic QFP (GF-3BA type) 64 PD78P0308, 78P0308Y * When using IE-78001-R-A as in-circuit emulator IE-78001-R-ANote IE-70000-98-IF-C In-circuit emulator common to 78K/0 Series products Adapter required when using a PC-9800 series (excluding notebook-type PCs) as the host machine (C bus supported) IE-70000-PC-IF-C Adapter required when using an IBM PC/AT compatible as the host machine (ISA bus supported) IE-70000-PCI-IF-A IE-780308-R-EM EP-78064GC-R EP-78064GF-R TGC-100SDW Note Adapter required when using a PC with an on-chip PCI bus as the host machine Emulation board to emulate PD780308 and 780308Y Subseries products Emulation probe for a 100-pin plastic LQFP (GC-8EU type) Emulation probe for a 100-pin plastic QFP (GF-3BA type) Conversion adapter to connect the EP-78064GC-R and a target system board made to be mounted on a 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Conversion socket to connect the EP-78064GF-R and a target system board made to be mounted on a 100-pin plastic QFP (GF-3BA type) ID78K0 SM78K0 DF780308 Integrated debugger for the IE-78001-R-A System simulator common to 78K/0 Series products Device file for PD780308 and 780308Y Subseries products (part number: SxxxxDF78064) Note Maintenance product (5) Real-Time OS RX78K0 Real-time OS for 78K/0 Series products Data Sheet U11776EJ2V0DS 65 PD78P0308, 78P0308Y (6) Precautions When Using Development Tools * The package name of the DF780308 is DF78064. * Use the ID78K0-NS, ID78K0, and SM78K0 in combination with the DF780308. * Use the CC78K0 and RX78K0 in combination with the RA78K0 and DF780308. * The NP-100GC, NP-H100GC-TQ, NP-100GF, NP-100GF-TQ, and NP-H100GF-TQ are products of Naito Densei Machida Mfg. Co., Ltd. (tel: +81-45-475-4191). * The TGC-100SDW and TGF-100RBP are products of TOKYO ELETECH CORPORATION. Contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (tel: +81-3-3820-7112) Osaka Electronics Department (tel: +81-6-6244-6672) * Please refer to Single-Chip Microcontroller Development Tools Selection Guide (U11069E) for information on the third party development tools. * The following table shows the software supported by each host machine and OS. Host machine [OS] Software RA78K0 CC78K0 PG-1500 controller ID78K0-NS ID78K0 SM78K0 RX78K0 PC PC-9800 series [Japanese Windows ] IBM PC/AT compatibles [Japanese/English Windows] Note Note Note TM EWS HP9000 series 700TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] Note Note DOS-based software 66 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Drawing of Conversion Adapter (TGC-100SDW) Figure A-1. Drawing of TGC-100SDW (for Reference Only) X C A B N L M T O X FED HIJK Protrusion height V W PQRS U G Y e a n m g I j i f h ITEM A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Z k d c b MILLIMETERS 21.55 0.5x24=12 0.5 0.5x24=12 15.0 21.55 INCHES 0.848 0.020x0.945=0.472 0.020 0.020x0.945=0.472 0.591 0.848 ITEM a MILLIMETERS 14.45 INCHES 0.569 b c d 1.850.25 3.5 2.0 0.0730.010 0.138 0.079 e f g h i j k l m n 3.9 0.25 0.154 0.010 3.55 10.9 13.3 15.7 18.1 13.75 0.5x24=12.0 1.1250.3 1.1250.2 7.5 10.0 11.3 18.1 0.140 0.429 0.524 0.618 0.713 0.541 0.020x0.945=0.472 0.0440.012 0.0440.008 0.295 0.394 0.445 0.713 4.5 16.0 1.1250.3 0~5 5.9 0.8 2.4 2.7 0.177 0.630 0.0440.012 0.000~0.197 0.232 0.031 0.094 0.106 TGC-100SDW-G1E 5.0 5.0 4- 1.3 1.8 C 2.0 0.197 0.197 4- 0.051 0.071 C 0.079 0.9 0.3 0.035 0.012 note: Product of TOKYO ELETECH CORPORATION. Data Sheet U11776EJ2V0DS 67 PD78P0308, 78P0308Y Drawings of Conversion Socket (EV-9200GF-100) and Recommended Footprints Figure A-2. Drawing of EV-9200GF-100 (for Reference Only) A B F M N E O R D C S K EV-9200GF-100 1 No.1 pin index P G H I EV-9200GF-100-G0E ITEM A B C D E F G H I J K L M N O P Q R S MILLIMETERS 24.6 21 15 18.6 4-C 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 INCHES 0.969 0.827 0.591 0.732 4-C 0.079 0.031 0.472 0.89 0.996 0.236 0.654 0.76 0.323 0.315 0.098 0.079 0.014 2.3 1.5 0.091 0.059 68 Data Sheet U11776EJ2V0DS Q L J PD78P0308, 78P0308Y Figure A-3. Recommended Footprints of EV-9200GF-100 (for Reference Only) G J K D L C B A EV-9200GF-100-P1E ITEM A B C D E F G H I J K L MILLIMETERS 26.3 21.6 INCHES 1.035 0.85 0.650.02 x 29=18.850.05 0.026 +0.001 x 1.142=0.742+0.002 -0.002 -0.002 0.650.02 x 19=12.350.05 0.026 +0.001 x 0.748=0.486 +0.003 -0.002 -0.002 15.6 20.3 12 0.05 6 0.05 0.35 0.02 0.614 0.799 0.472 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001 2.36 0.03 2.3 1.57 0.03 0.093+0.001 -0.002 0.091 0.062+0.001 -0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNT MANUAL" website (http://www.necel.com/pkg/en/mount/index.html). I H F E Data Sheet U11776EJ2V0DS 69 PD78P0308, 78P0308Y APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. U11377E U11105E U12251E This document U12326E Basic (III) U10182E PD780308, 780308Y Subseries User's Manual PD780306, 780308 Data Sheet PD780306Y, 780308Y Data Sheet PD78P0308, 78P0308Y Data Sheet 78K/0 Series Instructions User's Manual 78K/0 Series Application Note Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Assembler Package Operation Language Structured Assembly Language CC78K0 C Compiler Operation Language SM78K Series System Simulator Ver.2.30 or Later Operation (Windows Based) External Part User Open Interface Specifications ID78K Series Integrated Debugger Ver.2.30 or Later RX78K0 Real-Time OS Operation (Windows Based) Fundamentals Installation Project Manager Ver.3.12 or Later (Windows Based) Document No. U14445E U14446E U11789E U14297E U14298E U15373E U15802E U15185E U11537E U11536E U14610E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-78K0-NS-PA Performance Board IE-780308-NS-EM1 Emulation Board IE-78001-R-A In-Circuit Emulator IE-780308-R-EM Emulation Board Document No. U13731E U14889E To be prepared U13304E U14142E U11362E Documents Related to PROM Programming (User's Manuals) Document Name PG-1500 PROM Programmer PG-1500 Controller PC-9800 series (MS-DOSTM) Based Document No. U11940E EEU-1291 U10540E IBM PC series (PC DOSTM) Based Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 70 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U11776EJ2V0DS 71 PD78P0308, 78P0308Y NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC Electronics I2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. FIP and IEBus are trademarks of NEC Electronics Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. 72 Data Sheet U11776EJ2V0DS PD78P0308, 78P0308Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 J03.4 Data Sheet U11776EJ2V0DS 73 PD78P0308, 78P0308Y These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 |
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